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AD7767, SCLK on serial timing diagram

Question asked by usaghi on May 29, 2013
Latest reply on Jun 14, 2013 by usaghi

Hi,

 

The customer is asking on AD7767, serial timing diagram at Figure 3. and Figure 4., that they indicate SCLK of 23(Figure 3.) and 24(Figure 4.) pulses for reading 24 bits of data. Here, if we put 24 or more pulses in case of Figure 3., or 25 or more pulses in case of Figure 4., what could be occured ?

 

We are expecting there is no negative impact to operate AD7767, and whether we just read invalid data when after supplemental pulses, however please could you confirm.

 

Assuming, there is no daisy-chaining, 128KHz master clock, and 3.3V Vdrive, in their usage.

 

Best Regards, 

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