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PLL configuration... only works after hardware reset ...BF504F

Question asked by mDan on May 28, 2013
Latest reply on Jun 14, 2013 by mDan

Hey,

 

I've got a problem with the PLL configuration for the BF504F. I set up the registers and perform a bfrom_syscontrol(); command.

After that the PLL is still running with default values. If I perform a hardware reset (pulling the RESET pin to GND and back to VCC with a hardware button) the PLL will accept the new configuration and run with the frequencies I set up.

If I push the hardware reset button (so RESET has GND potential), power up the DSP and then release the button (RESET to VCC) the PLL won't work with the setup values. So basically, after powering up (and writing PLL registers via bfrom....) the DSP needs a hardware reset to set up the PLL properly... what could I have done wrong?

 

Hardware:

The RESET pin goes high ~1 second after powering up the DSP controlled by a voltage supervisor - but that shouldn't be an issue I guess.

 

Codesnippet:

 

#define VRCTL_VALUE         0x70B0              // enable extCLK

#define PLLCTL_VALUE        0x1C80              // CLKIN * 14 = (27MHz * 14 = 378 MHz)

#define PLLDIV_VALUE        0x0004              // CCLK = 378 MHz, SCLK 378 MHz / 4 = 94.5 MHz

 

#define PLLLOCKCNT_VALUE    0x0200

#define PLLSTAT_VALUE       0x0000

#define RSICLK_DIV          0x0001

 

u32 SIC_IWR1_reg;                /* backup SIC_IWR1 register */

 

 

/* use Blackfin ROM SysControl() to change the PLL */

ADI_SYSCTRL_VALUES sysctrl ={          VRCTL_VALUE,

                                                                                               PLLCTL_VALUE,                    /* (25MHz CLKIN x (MSEL=16))::CCLK = 400MHz */

                                                                                               PLLDIV_VALUE,                    /* (400MHz/(SSEL=5))::SCLK = 80MHz */

                                                                                               PLLLOCKCNT_VALUE,

                                                                                               PLLSTAT_VALUE };

 

 

SIC_IWR1_reg = *pSIC_IWR1;                                        /* save SIC_IWR1 due to anomaly 05-00-0432 */

*pSIC_IWR1 = 0;                                                                      /* disable wakeups from SIC_IWR1 */

 

/* use the ROM function */

bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_VRCTL, &sysctrl, NULL);

*pSIC_IWR1 = SIC_IWR1_reg;                                        /* restore SIC_IWR1 due to anomaly 05-00-0432 */

 

*pEBIU_AMGCTL   |= AMCKEN;              // enable extCLK

 

 

Thanks

Daniel

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