I am reposting this as the original thread ended up marked "answered" and thats an action that can't be undone
I have some exceptions associated with the instruction watch debugger that I need to analyse -- there are a couple ofpipleine hits that I am not expecting and I wanted to see if I could hand code the exceptions.
Trouble was -- I could get the instruction watch exceptions to activate in real life but not on the simulator.
Do either of the Blackfin simulators support the instruction watch or data watch operations?
If not, I will trigger the exception routines a different way and use the pipeline viewer then, but would be nice not to have to.
I then thought I had got into the instruction watch exception by "running" the simulator "for a long time", but it turned out that there was another problem that threw the exception.
Although I could not recover from what every exception the simulator thought had happened (in the same way that the real processor had recovered) , the fact that I got to the exception
enabled me to do the analysis on the timing of the exceptions and left me with two questions
Alot of the exception time was associated with the ssync( ) instruction which ended up being tranlated as cli r0; ssync, sei R0, which allows the ssync to proceed without being interrupted
Q1A -- should all ssync csync be treated the same way?
Q1B -- IS that process unnecessary in an exception since exceptions can't be interrupts?
Q2 Do the simulators support instruction watch operations and I did not managed to do something correctly?