Dear experts,I have a problem when using AD9633 interface with FPGA;
In my board, there are a FPGA of V6 and 4 ADCs with sampling rate at 80Mhz; I use the FPGA to configure the ADCs through SPI ports and capture the sampling datas.
I have finished the verilog code and generated the .bit file using the XILINX ISE software.When i program the .bit file into the FPGA device. I did 40 experiments(power on and power down) to test whether the code is right or not. i find only once or twice the result is wrong(the waveform is not smooth,it shows several burr. i use the ADC to sample the 1Mhz sine signal,i will post the waveform below), the rest experiments are right. Why the ADC are not stable?
i doubt 1. whether the configuration of the ADCs are right;
2. when the ADC output datas interface with FPGA, whether the FPGA internal logic is stable;
I am very confused by this phenomenon. i really need your help.