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ADV7403 output states when reset is asserted

Question asked by Eric_CMC on May 27, 2013
Latest reply on Jun 6, 2013 by Eric_CMC

What is the output state of video pixel bus and control signals when reset is asserted?: P0-P19, HS, VS, FIELD/DE, LLC1, SFL, INT. Are they tri-stated or set all low/high?