I'm designing a waveform generator with the new AD9102 device, and discovered that the data sheet does not clearly specify which edge of the SPI clock is active. There is a qualitative timing diagram in the "SPI PORT" section of the data sheet that seems to show that when writing to the device, data is transferred on the rising edge of the clock. Is this correct? If so, it is opposite from the convention for many Analog Devices DACs (including the excellent new AD5689R, for which I completed and tested a little circuit card just this morning). However, it appears that a lot of DDS chips use the rising edge of the clock, so I guess this might make sense for the AD9102/AD9106 as well.