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AD9910 Eval Board Sys_clk setup and sync_clk output

Question asked by harrycheung on May 22, 2013
Latest reply on May 23, 2013 by Kevin.G

Hi all,

 

I have been testing the Evaluation Board and is designing a new PCB for AD9910. I am trying to reproduce results of my custom board on the Eval Board. First, I want to set up the system clock. I power up the Eval Board, then connect a 100MHz 2V Vpp sine wave into the ref_clk, then I connect it with the computer with the software but I have not yet select the board on the software. I can see a 12.5 MHz, 1.6Vpp square wave on sync_clk, which is expected.

Then I do this again but without connecting to the computer. I power up the DDS and put in a 100MHz ref_clk. Then I connect the master_reset to logic high (3.3V) and then remove the connection. However, the sync_clk output is still zero.

 

My question is

How should I set up the system clock given that I have connected the ref_clk to a 100MHz signal? Is changing the master reset pin enough?

and

Do I need to do anything to see the f_sysclk/4 signal at the sync_clk output?

 

Thanks

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