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PLL Comparison PHR, EENotes, Expert Code Gen

Question asked by MarcZ on May 21, 2013
Latest reply on May 27, 2013 by MaheshN



I have some questions concerning the PLL Configuration. We are working on the ASDP21489 Ez-Board, on CCES.

I will give some examples and my questions will follow.


1 - The "pll_fromexample.c" comes from the 256_Point_FFT example.

Related to this, in the Hardware Reference Manual section 23-14, it is showing 2 methods of configuration. It looks like that in the example projects, the configuration is done with the first method from Step 1 to Step 6 and the second method then. It does not seem clear to me.


2 - The "our_pll.c" file comes from the EENotes :

These Example Codes show different way to configure the PLL, but different from the example projects.


3 - The "PLL.h" file is a part of the macro_cs.h of the Expert Code Generator for the 2148x processor.

It looks like the example projects but sometimes with a Bypass missing.


Also, sometimes I see simple loops and sometimes I see looping on "nop" which seems more reliable. But what is the best in C code?


Anyway, this looks not clear to me. Could you clarify and tell me what is the best PLL configuration?


Thank you,