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ADV7842 deinterlacing

Question asked by adhawkins on May 21, 2013
Latest reply on Sep 10, 2013 by adhawkins

Hi,

 

I'm experimenting with the interlaced to progressive conversion provided by the SD processor in the ADV7842.

 

I've managed to get it working with the eval board, but am having no luck with our platform.

 

Can you confirm what output format I should expect when applying the conversion to a PAL and NTSC input? Would it be 480p60, or 480p30 (and correspondingly 576p50 or 576p25)? Our processor is expecting 480p60 or 576p50 in this instance. The output I'm getting from the eval board when putting in PAL seems to be 576p50, but I just wanted to double check.

 

I've measured the clock frequency coming out of the 7842, and I was initially only getting 13.5MHz out (when I'd expect 27MHz). However, even using register 0xdd in the IO map to double this, I'm still not successfully capturing the input (although the clock is now running at 27MHz as expected). The VSync seems to indicate a 60Hz refresh rate also.

 

Can you offer any other suggestions?

 

Thanks

 

Andy

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