I have some questions about the output timing of ADV7619.
First, about the [Figure 4. Pixel Port and Control SDR Output Timing] of datasheet, would you answer to my questions in the attached Excel file?
Next, I know ADV7619 can shift the LLC phase against Data output using LLC_DLL_PHASE[4:0](IO map, 0x19[4:0]).
Please tell me the value (expected in design) of this register to tie in falling edge of LLC clock and transition point of Data output.
With best regards.