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AD9910 Eval Board PLL lock stability and output amplitude

Question asked by harrycheung on May 19, 2013
Latest reply on Jul 4, 2013 by harrycheung

Hi all,


I have been using the AD9910 Eval Board. I am using the on board 25MHz signal.I populated the PLL loop filter components. Their values are




I set the charge pump to 387uA. This should correspond to a open loop bandwidth of 50kHz.


The PLL is stable for a low multiplier value, e.g. x12. It becomes more unstable as I increase the multiplier value from 12 to 40. The PLL lock indicator of the software goes on and off as I go to higher multiplier value. I want to generate a variable signal of around 300MHz, is there a recommended loop filter for that. I tried the PLL filter excel file, but I don't know what does those values correspond to the performance of the PLL.


The PLL stability also seems to change with the output frequency, which I don't understand. When I run the DDS at single tone mode at multiplier (x32) and output 10MHz, the PLL is stable.But when I go up to 200MHz output, the PLL seems unstable. The PLL light of the software goes on and off. How could I stabilize it?


I have disconnected the filtered output. However, the unfiltered output seems too smooth. For a system clock 450MHz, and a output signal of 100MHz, I expect to see clear steps, instead I saw a smooth output. I want to use the unfiltered output directly, is there any way I can do so?


I checked the sync clk output, and found that it is unstable on an oscilloscope, especially at high frequency. Also ,the output amplitude of the sync clock decrease in amplitude when I increase the frequency. The actual unfiltered output also decrease in amplitude when I increase the frequency. Is it the characteristic of a DDS output?