I am using the AD9910 eval board. I am using the on board crystal (25MHz) and the multiplier(x40) to generate a 1000MHZ clock signal. However, I found that the PLL lock is unstable, which is indicated by the green indicator light of the software. I am using RC filter values R37=5ohm, C13=22uF,C15=2.2uF, which correspond to phase margin 45 degree, Icp=387uA, open loop bandwidth=4000. I am using a relatively low bandwidth because I want the system clock to be insensitive to the fluctuation of the crystal output. Will such PLL components cause the loop to be unstable?
Then I use a lower multiplier (x18) and get a system clock of 450MHz. I then generate a 10MHz signal which is fine, but the 100MHz signal (above graph) is not. The signal is actually changing in time. What could be the the reason and how could I solve it?