i try to use the DACs of ADAU1361 in slave mode with I2S input and have the problem that i get audio dropouts.
The datasheet states that this happens when i use the MCLK clock as CLKSRC source as LRCLK abd BCLK are unsynchronous to MCLK.
But i use the PLL and it still have audio dropouts.
I tried with 2 different PLL settings: 12.288MHz MCLK in integer mode and 27.000MHz MCLK in frational mode.
The only difference is that the dropouts are longer (abt. 20ms) with 27Mhz MCLK and only abt. 5ms with 12.288Mhz.
What can i do ?