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AD9834 - Constant Mclk/2 (37.5MHz) output

Question asked by Ale2k on May 14, 2013
Latest reply on Apr 16, 2015 by languer



I'm working in a project with an DDS AD9834 (Grade C). I used the idea of CN0156, controling the amplitude of the DDS output with an AD5660-1.

I followed AN-1070  to program the device, but the results aren't the expected ones.


The relevant information:






Note: The components marked as NL are not loaded in the board.


The supply voltage of the module is 3.3V for AVDD and 3.3V for DVDD.


The Mclk oscillator is  75MHz - 3V (ASFML1).


I took special care about the layout, following the guidelines in the datasheet and I used the AD9834 evaluation board (UG-266) as example. The ground planes AGND and DGND are connected with a single track under the AD9834.


I'm using a SPI bus with a variable word length (16-bit and 24-bit) to configure the DDS and DAC respectively.


The initialization words for the DDS at 1KHz are:








once initialized, to change the frequency, I send:





Note: The initialization is sent value by value (like was described before), but to change the frequency, I use functions to calculate this words. I checked that the 1 and 0 were correct.



The problem:


I have an output frequency of 37.5Mhz (Mclk/2) for most frequencies sent to the DDS, for the other ones the output is 0v.


I took some values that maybe help. If I send:


1 KHz   ---> Output=37.5MHz

2 KHz   ---> Output=37.5MHz

3 KHz   ---> Output=37.5MHz

10 KHz   ---> Output=37.5MHz

100 KHz   ---> Output=37.5MHz

1 MHz   ---> Output=0V

2 MHz   ---> Output=0V

3 MHz   ---> Output=0V

4 MHz   ---> Output=0V

5 MHz   ---> Output=37.5MHz

6 MHz   ---> Output=0V

10 MHz   ---> Output=0V


from 5MHz to 5.859374 MHz (with 1Hz steps) the output is 37.5MHz

from 5.859375 MHz (with 1Hz steps) the output is 0V (I didn't take more values to know if goes back to 37.5MHz).


Here are some plots of the output signal




...with other channel (a bit noisy but have level references)


TEK00013.bmp the 0v output




...and the Mclk








Actions taken:


I read all post referred to AD9834 and AD9833. There are 2 of them that users start with the same problem (   and  ). Seems they solved it but they don't say what exactly caused the problem. Anyway I followed the advices in the posts that are:


1- I reduced the REFOUT capacitor to 10nF (originally 100nF)

2- I haven't a FSADJUST capacitor

3- I haven't volatile pins (all inputs of DDS are tied to 1 or 0 by uC)

4- I met  timing diagrams from page 6 from Datasheet

5- I reduce the speed of SPI as much as I can (about 78KHz clock)


Here are some SPI plots








...with time references (FSYNC High to Low)




...with time references (FSYNC Low to SCLK Low )




...with level references




The strange thing is that the DAC (AD5660), connected in the same SPI bus, is responding correctly.

I have another DDS board with a AD9835 and it works ok (In replace of the AD9834 module).


Of course I adapt the supply voltage and bus levels when I change the modules (AD9835 --> 5V and AD9834&AD5660-->3.3V).


I also tried to over excite (increase supply voltage beyond the recommended) the oscillator (Mclk). The result is a greater level but a poor shape (looks like a triangular wave).


here is the plot






1- What's the min level for the Mclk? It is considered as an logic input? (page 4 - Datasheet)

2- If I supply 3.3V to AD9834, may I use a 5V SPI bus?, may I use a 5V Mclk? (page 7 - Datasheet)

3- If I supply 5V to AD9834, may I use a 3V Mclk?

4- The first page of datasheet say that is possible to use a 5V AVDD and 3V DVDD, but is contradictory with the “Absolute Maximum Ratings” in pag 7 (AVDD to DVDD -0.3V to +0.3V)

5- The Datasheet page 19 (DB13 Description)  say that two consecutive 28bits writes are not possible (using the B28=1). How I supposed to send 1KHz, then 1MHz and then 10MHz?

6- The most important, What can I do to obtain the desired frequency in the output instead the 37.5MHz?


Thanks for your time and please forgive me for my English.