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Digital lock detect problem on ADF4157.

Question asked by MakeMyDay on May 14, 2013
Latest reply on May 14, 2013 by MakeMyDay

I am using the ADF4157 fractional N PLL chip and have observed some strange behavior in the digital lock detect.

 

First, the operating conditions:

1) Frf = 1.68GHz

2) Fref = 12MHz

3) Fcp = 12 MHz (phase detector freq is the same as the reference clock)

4) Rcp = 5.6k (current setting resistor)

5) loop BW approx 30kHz

6) Kvco approx 50MHz/V

7) Integer modulus = 140

8) fractional modulus = 16777216 (2^24; i.e. frac freq = 1/4 ref freq)

9) R divider = 0

10) Neg CP bleed = off

11) CP current setting = 0

12) LD precision bit = 0

13) Vcp = 5V

14) Vdd = Va = 3.3V

 

Lock up and operation is OK with these settings (lock detect indicates a lock), but I notice a slow "traveling spur" moving up and down the rf output signal spectrum.  Turning on the Neg CP bleed bit removes this, but now the digital lock detect indicates that the PLL is not locked, even tho' it clearly is locked (from looking at the still rock-steady output tone spectral peak).  Playing with the CP current setting and current setting resistor and the LD precision bit have no effect.  The correct lock detect function returns only when switching off the CP Neg bleed bit.  Is there a fix for this?  The device in which the chip is used is set up for digital lock detect, so swithcing to analog lock detect is a bit of a problem.   Is there a workaround? Will this be fixed in later silicon versions?

 

Best regards!

Bill

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