I'm attempting to confirm the SPI Mode of the AD5122 Digital Pot.
It's noted/obvious in the datasheet that data is latched on the falling edge of SCLK.
What's not noted/obvious- is the "inactive" level of SCLK.
My 1st guess is that the inactive level for SCLK is logic-1.
If accurate, I'm assuming the required mode the SPI Master will need to operate at is Mode 2 (CPOL=1, CPHA=0).
Please, correct me if wrong.
Thanks in advance.