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SPI Mode for DigiPots (AD5122)

Question asked by TonyF@Vista on May 9, 2013
Latest reply on May 15, 2013 by DRice

Hi All,

 

I'm attempting to confirm the SPI Mode of the AD5122 Digital Pot.

http://www.analog.com/static/imported-files/data_sheets/AD5122_5142.pdf

 

It's noted/obvious in the datasheet that data is latched on the falling edge of SCLK.

What's not noted/obvious- is the "inactive" level of SCLK.

 

My 1st guess is that the inactive level for SCLK is logic-1.

Any insight?

 

If accurate, I'm assuming the required mode the SPI Master will need to operate at is Mode 2 (CPOL=1, CPHA=0).

 

Please, correct me if wrong.

 

Thanks in advance.

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