I had a question regarding the serial programming on the AD9959 DDS chip. Due to limitations in my SPI bus master, I am constrained to send 32-bit instructions and between every 32-bit instructions the CS goes high. Here is my proposal, tell me if it works.
The instruction cycle is 1 byte, but my host controller always sends out in 4-byte segments. For the first 3 bytes, I will send invalid instruction bytes (i.e. putting an address past the last register at 0x18, e.g. 0x3F). For the last byte, I will send the correct instruction byte. The first question is, how will the serial controller interpret these invalid instruction bytes?
After this instruction byte, the CS will necessarily go high (because of limitations in my SPI master). This is fine, the datasheet states "that cycle is suspended until CS is reactivated low." At this point, I will send the correct number of bytes of data (up to 4) corresponding to the register. If the correct number is less than 4, for example 2, I will again send the correct data for the first 2 bytes, but then send invalid instruction bytes to pad the transfer up to 4 bytes (again, because of limitations in my SPI master). If the serial controller on the AD9959 ignores invalid instruction bytes, I think this will work.
The last question is, I plan on tying the I/O Update to the CS. Hence, I will just be constantly I/O updating, sometimes in the middle of a <instruction + data> cycle. Will this interrupt the communication cycle?
Any help you can give would be great! Thanks in advance!