In my ezkit-bf609, link port-2 send data to FPGA, then FPGA return the data to link port-3. I test the linkport driver in core0, it works OK! Link port-2 sends data successfully, and Link port-3 recvs the right data.
Now, I copy the same code that works OK in core0 to core1, but In core1, link port-2 can't send data successfully, and link port-3 receives nothing. In the program of send data, the flag "bBufferComplete" keeps the value of "false", and "while" can't break. But in core0, it can break as bBufferComplete will change to "true".
/* Wait till the data transfer is over */
while(bBufferComplete == false)
eResult = adi_linkport_IsBufferAvailable(hDevice,&bBufferComplete);
As a junior to cces, I'm totally confused, and don't know what is the matter. I upload my project which can't send data in core1, and look for help.