There are "DATA AND CONTROL OUTPUTS(t11, t12)" in ADV7619 datasheet(Rev.B page.6).
What are the external conditions of t11 and t12 value? (e.g. load capacitor, resistor, etc)
The load capacitance and impedance are heavily dependent on the test board. We do not release this information. We strongly suggest using the IBIS models to determine the timing in your design.
The timing is based on our test configuration. The best way to determine timing in your system is to use the IBIS files. http://ez.analog.com/docs/DOC-1881
Thank you for your quick response.
I would like to know the condition(your test configuration) for "DATA AND CONTROL OUTPUTS(t11, t12)".
Because it means the timing between DATA and LLC, I think IBIS model is not suitable for this purpose.
The condition means the external load connected to Data pins and LLC pin, when t11 and t12 spec was determined.
Is that Open? Or how many is capacitance?
With best regards.
I heard with regret that you cannot provide it, but I understood.
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