Hi all, Currently trying to use the ADI reference HDL design for the ZedBoard for the AD-FMCOMMS1 and having issue with incompatible cores when I open the design in XPS. I am using the ISE 14.5 tool chain. The ADI documentation for the design is very limited and I am trying to view the system in VHDL or Verlog to start with. A simple block diagram on the Wiki would be very helpful
So I imported the x
The version management wizard reports
|Core Name||Current Version||New Version|
I suspect I need to regenerate the cores in the latest ISE Coregen prior to trying to import the files.
I will give it a go and get back
Okay, rebuilt the cores are suggested in the HDL portion of the wiki ,
I think the following instruction
"Once complete, copy the “*.ngc” files to the respective “netlist” and “*.v” files to the respective “hdl/verilog” directories. You may now open XPS and rebuild the project."
Needs to be elaborated further. Where are the "respective" directories located? Are they the ones under the cf_lib where we found the xco files or else where?