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Problems with porting to ISE14.5 tool chain

Question asked by wmaguire on May 7, 2013
Latest reply on May 15, 2013 by wmaguire

Hi all, Currently trying to use the ADI reference HDL design for the ZedBoard for the AD-FMCOMMS1 and having issue with incompatible cores when I open the design in XPS.  I am using the ISE 14.5 tool chain.   The ADI documentation  for the design is very limited and I am trying to view the system in VHDL or Verlog to start with.  A simple block diagram on the Wiki would be very helpful

 

So I imported the x

 

The version management wizard reports

 

 

Core Name
Current VersionNew Version
processing_system3.00a
4.03a
axi_hdmi_tx_16b
1.00a
REMOVED
axi_spdif_tx
1.00a
REMOVED
axi_dma
5.00a
6.03.a
axi_clkgen
1.00a
REMOVED
axi_dac_4d_2c
1.00a
REMOVED
axi_adc_2c
1.00a
REMOVED
util_outclk_lvds
1.00a
REMOVED

 

 

I suspect I need to regenerate the cores in the latest ISE Coregen prior to trying to import the files.

 

I will give it a go and get back

 

Regards

 

 

Walter

 

 

Okay, rebuilt the cores are suggested in the HDL portion of the wiki ,

 

http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl

 

I think the following instruction

"Once complete, copy the “*.ngc” files to the respective “netlist” and “*.v” files to the respective “hdl/verilog” directories. You may now open XPS and rebuild the project."

 

Needs to be elaborated further.  Where are the "respective" directories located?   Are they the ones under the cf_lib where we found the xco files or else where?

 

Regards

 

Walter

 


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