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Unable to serial programme AD9959. Any suggestions?

Question asked by Chris_B on May 2, 2013
Latest reply on May 22, 2018 by Tanzir

Hi All,

I'm unable to communicate with the AD9959/AD9959PCB and I'm unsure where I'm going wrong. The AD9959 appears to work correctly when using the UBS interface and supplied software but as I'm trying to operate it via Labview on a win 7 PC I need to use manual control and so I'm currently using a USB DIO card to generate digital signals of 5V, 0.5us rise time, at 60Hz.

 

I'm using 4 DIO channels connected to IO_update, SCLK & RESET on header U2 and SDIO_0 on U13. Jumpers W10, W1, W2, W3 have been removed and W7 set to manual. CSB, PWR_DWN, SDIO_1, SDIO_2 & SDIO_3 on header U2 are connected to ground. All other header pins are floating. W4, W5, W6 jumpers are also removed. W9 connected.

 

Ultimately I'd like to independently control the amplitude, phase and frequency of each channel so I believe I need to set the chip in single tone-mode with no modulation. Thus I initially send a reset bit followed by the following to SDIO (with concurrent SCLK signals):

 

Instruction byte 0x00

data byte 0xF0

Instruction byte 0x01

data byte 0xD0

data byte 0x00

data byte 0x00

Instruction byte 0x02

data byte 0x00

data byte 0x00

Instruction byte 0x03

data byte 0x00

data byte 0x03

data byte 0x20

 

The above is then followed by an IO_update bit (no SCLK signals with reset or IO_Update).

 

After this I send the frequency, phase and amplitude to each channel, followed by another IO_Update bit (after all channels registers have been written). For example, to program channel 0 at max frequency (25Mhz x 20 = 500MHz), min phase (0) and max amplitude (AVDD+0.5V = 2.3V) I send the following (again with concurrent SCLK signals):

 

Instruction byte 0x00

data byte 0x10

Instruction byte 0x04

data byte 0xFF

data byte 0xFF

data byte 0xFF

data byte 0xFF

Instruction byte 0x05

data byte 0x00

data byte 0x00

Instruction byte 0x06

data byte 0x00

data byte 0x13

data byte 0xFF

 

the above is then repeated with first data byte changed to 0x20 (or 0x40, 0x80) and subsequent data bytes set as required for the desired frequency, phase and amplitude of each channel. Finally a IO_Update bit is sent.

 

The timing of the DIO channels appears correct when viewed on an oscilloscope; e.g. SDIO is high when SCLK changes from low to high (i.e. write to register) for 1, bytes are sent as MSB to the AD9959/PCB, IO_Update follows SDIO commands etc.

 

I'm not sure what, if anything, else I need to send or trigger and when these additional things should occur. Any suggestions/comments would be greatly appreciated.

 

Thanks in advance,

Chris

 

Message was edited by: Chris Baker The problem has been identified as being due to the SCLK timing. A 50% duty cycle doesn't work whereas a 33% duty cycle does: Example: Didn't work SLCK 01010101 SDIO  11001100 Works SCLK 010010010010 SDIO  111000111000

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