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AD9957 interface to 1.8V FPGA

Question asked by roadrunner Employee on May 1, 2013
Latest reply on May 8, 2013 by DSB

Is it possible to lower DVdd_io to 1.8V or some lower value than 3.3V nominal that will allow me to interface to Virtex 7 FPGA 1.8V level I/O lines.  If not, what is the best way to handle this logic level translation?