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AD9915 PLL Loop Filter

Question asked by DBon on May 1, 2013
Latest reply on May 10, 2013 by DSB



I am currently looking at a design that will use the AD9915 DDS. Looking at the datasheet, it recommends the use of a 560pF cap across pins 58 and 59 (Loop_Filter and REF respectively) with a 0.22pF cap to ground. However when looking at the schematic for the Eval board (noting that the actual schematic is for the AD9914 Eval Board as one for the AD9915 is not available) the components used differ to the ones mentioned previously. Instead it has been opted that the use of a 560pF (C100) is in parallel with a 43pF cap (C101) which is in turn in series with two  parallel 0.22uF caps to ground.


Please could you advise which is the correct method? And if you recommend the use of the 0.22pF cap would it be OK to use pad capacitance between parallel plates on the board?