I have a two processor design Both U1 and U2 are ASuC841s and there are 4 other SPI components on the SPI bus, Both are run by a 8 Mhz clock, U1 is master and U2 is slave. The bus transfer rate is limited to 500,000 hertz due to a very slow rise time on the Din and Dout lines, the clock is fine even at 4 mhz. I assume the max viable speed for the SPIbus between the processors is 4 Mhz but alas it is not the case. I tried a 2.2 k pull up, but all that happens is raise the low level basis and does not change reduce the rise time from low to high at all. The next step is to only populate the two processors and test the xfer signal integrity at 4 MHZ. Is there anything I need to know to reduce the implied impendence so the rise time will be much much faster?