I am having some issues with the stability of the ADF4351's used as LO's on the ADI FMC FCOMMS1 board. Occasionally at power on or with a large LO, ADF4351, frequency change one of the ADF4351's appears to become unstable on the FCOMMS1 board being used with Xilinx ZC702 board.
I would like to get some feedback and comments from a person at ADI that understands the ADF4351 from an analog design point in regards to its circuit on the FCOMMS1.
I have the FMCOMMS1 configured to look at its TX output from RX input with 20dB pad and DC block in the path. I am using the ADI OSC application in Frequency Domain mode to look at the default 40MHz DDS output tone from the TX side.
At times after a power on or with large ADF4351, LO, frequency change the default fundamental 40MHz DDS tone amplitude on the Linux ADI OSC application in Frequency Domain mode is unstable and jumps around about 1dB. On the other hand if everything is stable the fundamental DDS tone only varies about .02dB on the OSC application in Frequency Domain mode.
The FCOMMS1 design has two ADF4351's one for TX LO and one for RX LO. It normally seems to be the TX ADF4351 that most always comes up in some mode that shows this given instability when it occurs.
I have done some testing to determine that this seen instability on the FCOMMS1 is due to the ADF4351 doing “something funny”. Using the base IIO commands I wrote some scripts to toggle the TX or RX ADF4351 reg2 power down bit off then back on. Most often running the script that toggles the TX ADF4351 reg2 power down bit off then back on will fix the unstable operation and in the ADI OSC application in Frequency Domain mode the fundamental DDS tone stops jumping and be comes stable to within about .02dB
To follow on with this I rewrote the ADF4351 IIO Linux driver such that it also allows me to turn on and off the reg2 counter reset bit or reg4 VCO power down bit along with scripts to toggle them off and back on.
What I have found is typically toggling the TX ADF4351 reg2 counter reset bit will most often fix the given unstable output issue just like toggling the TX ADF4351 reg2 power down bit does.
From a circuit design view the ADF4351 loop filter on the FCOMMS1 uses a large 1uf and small 32.4 ohm resistor on the charge pump output. These cap and resistor values are very different from the basic ADF4351 reference design which uses around .039uf and 320 ohm on the charge pump output.
Can someone comment on the use of these 1uf and 32.4 ohm values for the ADF4351's on the FCOMMS1 as to what this does andwhy they are so different from the basic reference design ADF4351 values. (Also as used on FMC AD9739 board.)
I have read over the ADF4351 data sheet and application notes. I can not find any information in regards to cap and resistor selection for the charge pump. The ADF4351 data sheet provides little descriptive information as to what various register bit settings full do also. I see nothing in regards to what the proper settings of the charge pump current should be for a given load etc..
I would really like a person a ADI to aid in determining if the FMCOMM1 circuit for the ADF4351 is valid and stable?
Is there a issue with the ADF4351 Linux driver, which I have studied, that might be changed to eliminate the unstable output problem on the FCOMMS1 that I am seeing when using with the zc702?