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Regarding ADSP-BF53x_EZ_KIT_Lite Layout

Question asked by 218024828 on Apr 30, 2013
Latest reply on Aug 29, 2013 by 218024828

Is there any documentation talking about the multiple drop bus layout of blackfin processor? for example within a multiple processors system the blackfin will share bus with other processors (be ware this is not a single processor to use multiple memory like 1 Processor+2 DDR), to properly terminate the bus will ensure the system reliability.

 

1. I checked the ADSP-BF53x_EZ_KIT_Lite_Layout.zip, the blackfin ezkit didn't use any terminations to interface sdram/flash bus, nor

on the layout. The ezkit layout has many vias along a bus line, which you can say is unavoidable, fine, but a better practice like termination

should be implemented.

 

2. there are daisy-chain + end termination, star, or T termination for multiple drop bus layout, does Analog Devices provide some

recommendations?

 

3. Unlike the VME or PCI backplane shared bus layout, the blackfin + multiple processors + shared bus should have an easier layout.

Do we need to borrow technique from other backplane design?

 

give us some suggestions. thanks.

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