I have a AD7091R application which is outputting 'improperly justified data' at lack of a better description. The first bit shifted out doesn't appear to be the MSB, rather the results of a previous conversion - the 8th bit shifted out appears to be the MSB of a new conversion.
Here's a scope shot of the ADC when it's running, with a DC input that's slightly less than half scale. Top trace is /CONVST, second trace is DATA, 3rd trace is SCK and fourth trace is /CS. You can see the "LSB wiggle" happening on the 6th and 7th clocks read out.
I am performing a reset on the ADC, as the datasheet suggests - here's a scope shot of the procedure. I keep the readout clock active but bring /CS high early.
Some other notes on the design:
-VDD is 3.3V, REFIN is tied to the same rail as VDD.
-VDRIVE is a separate 3.3V rail
-Timing is generated with a CPLD clocked at ~40MHz, the SCLK clock rate is 20MHz.
With the CPLD in reset, /CS and /CONVST are high, and SCK is low. When the CPLD is taken out of reset, CPLD reading begins at a ~720KHz sampling rate (~40MHz/55) and /CONVST goes low before anything else happens. During the first read from the ADC, /CS is set high early as shown above in the second capture. Subsequent reads have the /CS line driven normally as shown in the first capture.
I've been through the datasheet many times, trying to find something I've done wrong, but I can't find anything obviously wrong.
Any suggestions? Thanks!