I'm working on a program that mainly access the external SDRAM via DMA and chained DMA accesses.
Well so far it seems to work, but now I only need to read four words from SDRAM instead of bigger blocks. I found out (by cycle count measurment) that a core access needs less cycles then DMA access at that moment. But it seems not to work always. Sometimes I have wrong data. I tried already to set/clear some bits in the DMAC0 register and to clear the CPEP register but it did not help. So my question is: How can I mix DMA, chained DMA and core access for reading from SDRAM on a 21369?