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PLL generating and distributing

Question asked by FredT on Apr 25, 2013
Latest reply on Apr 25, 2013 by Kyle.Slightom



I need a PLL that allows me to do something like the previous image. The OUT5, OUT6 and OUT7 clock would be generated by an Internal VCO. I thought I could do this with the AD9517 but it seems that the VCO clock must be sent to all outputs when it is used. Since I have limited space I almost certainly need this solution to be on one chip only.