I posed these questions and received answers which are shown inline with the original questions:
I am currently working on getting the I2S input on the ADV7623 working. The HW reference manual provides some steps to perform but I have a few further questions:
1) We have MCLK available as an input, but the HW ref. manual says it is optional for I2S input operation. I see that TX Main Map 0x0B bit 5 allows you to select internally generated or externally generated MCLK. Right now the default is internal – but I don’t see where that value is established? Or, what determines the internal MCLK value?
A: The ADV7623 can generate it’s own internal MCLK based on the incoming audio. External MCLK is required however, for HBR audio when the audio is transmitted via SPDIF (as opposed to I2S).
2) Is MCLK ratio (TX MAIN MAP 0x0A bits 1:0) meaningful for both internally and externally available MCLK?
A: The MCLK ratio must be set appropriately (128X, 256X etc) depending on the ratio of the incoming MCLK to LRCLK frequencies.
3) Page 142 of the Mar’10 SW reference manual shows that I2S_EN is for “AP3_IN” pin. This seems like a typo to me, because I2S_EN also says it is for “AP3_IN” pin. In an older reference manual we see that AP1_IN should be used for I2S two channel – is this correct? And should I set I2S_EN to use AP1_IN?
A: Yes, all correct.
4) Is there any issue with having the SPDIF receiver enabled at the same time as having I2S enabled (i.e. can TX MAIN MAP 0x0B bit 6 be set for SPDIF receiver enabled, and I2S_EN[3:0] be set at the same time?) – You can only select one input mode at a time via TX MAIN MAP 0x0A bits 6:4 so I am thinking this may be safe?
A: Yes, this is okay to do.
5) TX MAIN MAP 0x0C bits 7 and bits 6 in the SW manual say they are applicable for “I2S mode 4” – what is mode 4? I don’t see any reference to it in the manuals? If these bits are set to ‘1’ are they only meaningful in mode 4? How and where do I set the mode as related to the “mode 4”?
A: It’s an error that should read “mode 3”, and refers to I2SOUTMODE bits [1:0] being set to 0b11, indicating Raw SPDIF (IEC 60958) mode.
6) Another question with the 0x0C bits 7:6, if they have a value of 0, the SW manual says “use sampling frequency from the I2S stream” and “use channel status bits from I2S stream” – that sounds kinda SPDIF-ish, how does it use sampling frequency and channel status bits from the I2S stream?
A: This is explain in the I2S Audio section of the ADV7623 HW manual. When the manual talks about using the sampling frequency from the the I2S stream and using the channel status bits from the I2S stream, it is talking about using direct AES3 stream I2S format. Otherwise, these bits can be set to 1 and manually programmed.