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ADF4106 Digital Lock Detect

Question asked by TimW Employee on Sep 29, 2009
Latest reply on Oct 1, 2009 by BobC

1)We need to know from Analog Devices if loading the ADF4106 Digital Lock Detect with a 1uF capacitor would compromise the performance or reliability of the ADF4106.

 

2)  Given the PLL parameters that I have listed above, such as setting a 10 nsec Digital Lock Winodw, waiting 3 or 5 consecutive phase detector cycles, the PLL/VCO locking within 50usec which is a function of the loop filter bandwidth, and PFD frequency (not defined) can you find any reason why we cannot directly interface a CMOS VHDL device to the ADF4106 Digital Lock Detect signal?

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