I have asked from one costomer that unexpected leaps are observed on output of AD9257 at a few channels, as shown in attached bitmap.
Vertical axis is ourput data, and horizontal axis is timeline and number of sampling. Ch.4 and Ch.5 show sudden leaps bound over 8200, despite input level is not so changed.
The customer also add comment that Ch.6 and Ch.7 are also invalid, because it must not be below 8192.
Output is received at FPGA, and the customer said it seems FPGA can see normal input when receiving test pattern from AD9257.
The customer provided layout pattern, as I attached.
They also provided schematics but I assume it should send to you in closed loop.
I assume it is a bit difficult to point out what is occured by these restricted information, however if you can have a hint what could be a cause to such output, it would be much appreciated.