I am using the DSP21369 Sharc. I am reading the data sheets for an ADC (AD7367-5) and a DAC (AD5754). They both can take SPI or SPORT interfaces. Is there any advantage of SPI over SPORT?
You could use both SPI and SPORTs for the interface. Both has its own advantages and disadvantages. SPI peripheral inherently provides gated clocks whereas in the case of SPORTS the clock is continuous. Sports can be configured for variable data length . For the AD7367 they can be configured for word length of 14 directly whereas SPI can only be configured for 8,16,32 bit word lengths. When using SPI it has to be configured for 16 bits and padded with zeros for interfacing with the 14 bit CODEC and hence reduces performance
Please take a look at the following application notes which discuss similar interfaces.
I have worked through the same question. The biggest difference is that the SPORT Clock runs continuously, which many ADCs don't like. The Frame can be used sort of like a Chip Select, but if you need a delay between /CS and CLK, you can't get it from the SPORT. On the 2136x, the SPORT is not bi-directional, you need to use 2 channels to get SPI-like duplex handling. Conversely, the SPI ports don't allow DMA in both directions. Also, the SPI is limited to 8/16/32bit transfers, which may not meet your needs.
In general, I think the SPI is more compatible with most ADCs. There are a couple (I haven't looked up your devices) that claim to be "DSP compatible" but read carefully. Some of those are simply SPI Masters which generate an external Clock. SPORTs are better if you need duplex with DMA, but check the timing. I've used the Frame to gate the Clock to avoid the overrun issues.
I am curious to read the official response.
In many cases, the choice may be based on the number of DAI versus DPI pins that you have available or the available SPI versus SPORT resources.
You can make a SPI Master from a SPORT fairly easily.
I used to do this with old ADI DSPs before they all had SPI ports. I have attached a schematic of a circuit that I used back then (and I haven't looked at it for years).
You do need to skew the SPORT CLOCK a little. The attached schematic achieves both SCK gating and the timing skew. I used a 74LVC02 NOR (or just about any convenient logic). The inverter is required for delay so don't let logic minimization remove it in a PLD or FPGA implementation
I think the circuit achieves SPI Mode 1,1 (3) which is the most common. You can modify the circuit a little to get other SPI modes. SPI Mode 0 & 3 are used in 99% of the cases I've seen.
So you can take into account that The SPORTS are ready to transmit or receive two serial clock cycles after enabling. So two waste seraial clocks aren't need for ADC as SAR (AD7687, AD7685 and etc)
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