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Asynchronous Memory & ARDY

Question asked by max@003 on Apr 23, 2013
Latest reply on Apr 25, 2013 by Nabeel

Hi All,

I am facing an issue with BF533 and AMS interface, the issue is not about interface not working, but about my understanding.. I wish you guys can help me get my doubts cleared

 

This is how hardware is placed out - a 45 ns SRAM is connected to AMS0, a Flash memory is connected to AMS1 (comes into picture only during start up) and another ASIC is interfaced as external memory on AMS3

 

AMS0/AMS1 do not use ARDY and they are configured (EBIU_AMBCTL0 ) with something like 4 read / write cycles, 1 setup,1 memory transition ND ARDY disabled

 

where as AMS3 (ASIC) is configured with 3 read / write cycles 1 hold, 1 setup,1 memory transition time and ARDY enabled.

As per ASIC specification XRD pulse width should be 115ns and XWR pulse width 83ns, BF533 is running at 98 Mhz.

Though XRD/XWR pulse width are not matched ARDY must be taking care of it.

is my assumption is correct?

 

ASIC- BF interface is working fine in most of the cases but on certain boards I am facing some memory corruption

 

Second, is this memory corruption (1-2 bytes at same location) can be timing related?

(the memory corruption is observed only in 1-2 boards out of 10, in total I have almost 12 such faulty devices with me)

 

While working on timing I found if I set AMS3 (EBIU_AMBCTL1) with 0xFF55, i.e. 15 read / write cycles few of these faulty units do work properly.

 

But I am worried if I keep AMS3 with 15  read / write cycles, will it affect the SRAM performance?

 

I am not sure if i was able to explain my situation completely, please let me know if any more inputs are required.

Any help would be really appreciated.

 

Regards

Max

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