We are assuming what would be occured when power supply from primaly side is stopped by any reason during operation, for example, malfunction at internal or external circuitry, at ADuM5402.
In this case, how is the state of primary/secondary side of output pins supposed to be ?
Subject to page.24 of datasheet, POWER CONSIDERATIONS, we are assuming output become to be high-impedance, but it can allow to understood that it may be default low, or remain state just before power down.
Especially following last phrase are not clear to see...<The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO.>
If you provide another explain by focusing a case power supply suddenly stop during normal operation, it would be very much appreciated.