After a few days spent on trying to interface AD9467 to FPGA. I found that there is a difference in AD9467 datasheet revisions.
Rev.C has SPI register 0x17 (output_delay)
Rev.D has no information about output delay adjustment.
Only after trying to adjust this register, sensible data from AD9467 started to come out.
Why there is no information regarding output_delay adjustment mentioned in Rev.D datasheet?