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AD9467 output delay

Question asked by Danielius on Apr 23, 2013
Latest reply on Apr 30, 2013 by UmeshJ

Hi,

 

After a few days spent on trying to interface AD9467 to FPGA. I found that there is a difference in AD9467 datasheet revisions.

Rev.C has SPI register 0x17 (output_delay)

Rev.D has no information about output delay adjustment.

 

Only after trying to adjust this register, sensible data from AD9467 started to come out.

Why there is no information regarding output_delay adjustment mentioned in Rev.D datasheet?

 

Thanks,

Best Regards,

 

Danielius

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