Does ADI provide the VHDL/Verilog(Source) code for the ip needed to interface with JESD204x ADI ADC converters? Thanks for your support.
We provide reference designs that uses Xilinx IP (JESD-IP) that are publicly available (see links below). The IP itself is not free and no source code is available. Though it definitely needs some work, replacing the IP is relatively very easy. You only need to do data alignment (you can do this also in GTX), (de)scrambling and (de)framing. All the difficult stuff on the high speed side are taken care by the GTX/H/P primitives.
The following will provide a reference point to start with.
Thanks Rejeesh for the response. It would be helpful to put the modified example of the Xilinx Logic core modules that you mentioned.
We have no plans to make any modifications, if you ran into problems using any of the reference designs that I mentioned, please let us know.
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