what go external pin mode,global clock mean in ADC9650?
The AD9650 has many configurable features, typically controlled through register writes. The AD9650 does allow some features to be configured without register writes. If a user does not have SPI access, they can force CSB pin high (tie to AVDD) and then configuration control outlined in Table 15 occurs. The SDIO/DCS pin controls the Duty cycle stabilizer, SCLK/DFS pin controls Output data format, OEB and PDWN pins can also be used to disable the output and force power down mode.
Regarding your question about “Global Clock” this refers to features that impact both ADC’s, for example Duty cycle stabilizer is either enabled or disabled for both paths simultaneously.
thanks for your useful answer.
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