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One error (about Mode1 regeister) in ADSP-2136x SHARC Programming Reference?

Question asked by zooho on Sep 25, 2009
Latest reply on Sep 25, 2009 by DivyaS



I am reading the ADSP-2136x SHARC Programming Ref and found the Figure B-2 of Mode Control 1 Register bits 15-0 shows:


Secondary Registers Register File High Enable
1=Enable R15–R8 primary
0=Enable R15–R8 secondary



But if check the 2-40 of the same document, you can find the following:


The MODE1 register controls the access to alternate registers. Table B-2 on
page B-5 lists the bits in MODE1. The following bits in the MODE1 register
control alternate registers (a 1 enables the alternate set):
• Secondary registers for computational unit results, bit 2 (SRCU)
• Secondary registers for the hi register file, R8–R15 and S8–S15, bit 7
• Secondary registers for the lo register file, R0–R7 and S0–S7, bit 10


Which one is correct? I think the Figure B-2 is wrong and need to be corrected from 1 = enable primary ===> 1 = enable secondary for those bits of SRRFL, SRRFH, SRD2L, SRD2H, SRD1H, SRD1L and SRCU.