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AD9467FMC+Zedboard HDL reference design bitstream

Question asked by sgphoto on Apr 10, 2013
Latest reply on Apr 14, 2013 by rejeesh

Hi,

 

I had a AD9467FMC and Zedboard. I followed the instructions in http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467, the ADC tests are all passed when using the pre-built bitstream file. However, when I try to build the bitstream on my own, there is one error which stops implementation.

When create a new project, and add embedded sources, I just add subdesign from the HDL reference design, the system.xmp.

I am using Planahead 14.4, and the HDL reference design is cf_ad9467_zed_edk_14_4_2013_02_11.tar.gz.

The error and critical warnings are as follows:

  • launch_runs impl_1 
  • [Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_???' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_axi_interconnect_1_wrapper.ncf":6] 
  • [Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_????' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_axi_interconnect_1_wrapper.ncf":7] 
  • [Constraints 18-11] Could not find cell or net 'axi_interconnect_2/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_???' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_axi_interconnect_2_wrapper.ncf":6] 
  • [Constraints 18-11] Could not find cell or net 'axi_interconnect_2/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_????' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_axi_interconnect_2_wrapper.ncf":7] 
  • [Constraints 18-11] Could not find cell or net 'U0/*/U_STAT/U_DIRTY_LDC' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_ila_0_wrapper.ncf":5] 
  • [Constraints 18-11] Could not find net 'U0/U_ICON/*/iDRCK_LOCAL' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":1] 
  • [Constraints 18-11] Could not find net 'U0/iUPDATE_OUT' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":4] 
  • [Constraints 18-11] Could not find net or pin 'U0/iSHIFT_OUT' ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":5] 
  • [Constraints 18-47] TIMESPEC TS_adc_clk_in_p is redefined. The earlier version defined at (file = system.ucf, line = 29) will be discarded ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/data/system.ncf":29] 
  • [Constraints 18-47] TIMESPEC TS_adc_clk_in_n is redefined. The earlier version defined at (file = system.ucf, line = 31) will be discarded ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/data/system.ncf":31] 
  • [Constraints 18-329] No definition for group 'D2_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_ila_0_wrapper.ncf":6] 
  • [Constraints 18-329] No definition for group 'D2_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_ila_0_wrapper.ncf":7] 
  • [Constraints 18-329] No definition for group 'D2_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_ila_0_wrapper.ncf":8] 
  • [Constraints 18-329] No definition for group 'D2_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_ila_0_wrapper.ncf":9] 
  • [Constraints 18-329] No definition for group 'U_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":6] 
  • [Constraints 18-329] No definition for group 'U_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":7] 
  • [Constraints 18-329] No definition for group 'J_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":8] 
  • [Constraints 18-329] No definition for group 'J_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":9] 
  • [Constraints 18-329] No definition for group 'J_CLK', timing constraint is ignored ["D:/xilinx144_prj/AD9467FMC/AD9467FMC.srcs/sources_1/edk/cf_ad9467_zed/implementation/system_chipscope_icon_0_wrapper.ncf":2] 
  • [Chipscope 16-30] There are 24 unconnected channels on debug port 'system_i/chipscope_ila_0/chipscope_ila_0/i_chipscope_ila_0/control'.  This may cause errors during implementation. 

 

Please help me to identify what is the reason, and how I can generate my own bitstream. I may add my own logic based on this reference design.

 

Best Regards,

Cao Bin

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