I am planning a data capture system with AD9286 ADC and HSC-ADC-EVALDZ capture board.
The reason why I choose HSC-ADC-EVALDZ instead of HSC-ADC-EVALCZ is that Xilinx Virtex-6LX75 on the board can be dealt with free Xilinx ISE webpack. I mean that I will add some custom logic circuits to the FPGA.
Then I have some questions.
1. Can HSC-ADC-EVALDZ be used with AD9286-500EBZ evaluation board?
I think HSC-ADC-EVALDZ is the superset of EVALCZ concerning ADC and Capture board connection. Is this correct?
2. How many slices of Xilinx FPGA are occupied by ADI capture logic circuit in v6 FPGA?
How many slices are the room in v6 FPGA? If the room is little for me, I have to change the plan.
3. Where can I get HDL codes of HSC-ADC-EVALDZ? Are they included with HSC-ADC-EVALDZ package?
Thanks in advance.