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NFC Boot

Question asked by Varun-Blackfin on Apr 10, 2013
Latest reply on Apr 16, 2013 by Prashant



I have a query based on Pg. 17-88 of BF54x Hardware Reference Rev. 1.2 in following paragraph:


Providing OTP configurations of  RD_DLY  = 0x0 and  WR_DLY  = 0x0 will result in the boot kernel  using the default configuration of

RD_DLY  = 0x3 and  WR_DLY  = 0x3. The highest performance settings for NAND flash boot are enabled with  WR_DLY  = 0x1 and  RD_DLY  = 0x0.


1. What is the meaning of highest performance settings?

2. What will be number of read and write cycles based on setting WR_DLY  = 0x1 and  RD_DLY  = 0x0.?


In boot flow diagram Fig 17-, BMODE pins sampling are not shown in any of the boxes in the flow, at what stage in boot procedure does BMODE pins are sampled?


Thank You