We are sending a 64 word packet via Link Port from one 21469 to another 21469.
The clock is set to Core Clock/4 (112.5MHz)
SPORT DMA is also running. We actually start sending the 64 word packet from a SPORT TX interrupt. There is sufficient time allowed between SPORT interrupts to transmit the whole packet. All code is in assembly. We are using Rev 0.2 silicon.
We can send several thousand of these packets without problems but sometimes it faults.
If we monitor LSTAT0 and set a trap (breakpoint) on an error condition, we observe that both the packing error bit (LERR) and DMACH_IRPT are both set. When this condition occurs, the DMA count (CLB0) is non zero. Nevertheless, the interrupt handler was called .
Can someone explain what mechanism inside the 21469 actually sets the packing error flag?