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Why EPPI0 Receive fail above EPPI0_CLK=13MHz (SCLK=130MHz)?

Question asked by BFProgrammer on Apr 8, 2013
Latest reply on Apr 23, 2013 by BFProgrammer

Hi All!

Configuration:

BF547 board (CCLK=520MHz, SCLK=130MHz). GP 1 FS mode, Word16bit data.

DSP receiving data from FPGA through EPPI0, using EPPI internal clock, FPGA uses 150MHz clock to sample the EPPI clock.

and transfer data in the same rate as clock with shifted timing, the data and clock at the output of the FPGA  lookes OK.

 

With such a configuration, EPPI  can communicate with up to SCLK/2=65MHz theorecal speed, as stated in BF54x Hardware Reference.

But in reality the flawless receive is got only at 13MHz, while at 16.25MHz the receive starts to fail getting sometimes double the same word16 data.

 

     Note: This is the mine EPPI0_CONFIG:

 

 

//(1<<4) FS_CFG - GP 1 FS Mode, BLANKGEN=0, Receive mode

//(4<<15) DLEN: means 16bits.

//(0<<11) POLC (FS, Data Driving, and Sampling Edges) 00 - Sample data on falling edge and sample/drive syncs on falling edge

//(3<<13) POLS : 11 - FS1 and FS2 are active low

 

*pEPPI0_CONTROL = XFR_TYPE | (1<<4) | (4<<15) | ICLKGEN | IFSGEN | (3<<13) | (0<<11) ;

 

Peter.

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