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Video Demystified - Incorrect 480p Timing? Or am I missing something?

Question asked by MrBEEF on Apr 5, 2013
Latest reply on Apr 17, 2013 by MrBEEF

GuenterL & MattP,


How's it going guys? So after doing multiple projects, I am back on this pan/zoom project, using the Xilinx ML605 development board and the AVNET HDMI FMC card, whic use both the ADV7511 and the ADV7611.


So using the Video demystified book as GuenterL suggested, I wrote quick verilog test pattern generator. The FMC card with the ADV parts, using embedded syncs, 16-bit, YCbCr, Left Justified setup. I use a Microvision Pico Projector (HDMI in small projector), which takes in 480p. So I started developing the test pattern, got it running and I got nothing. Check register set...everything looks good, then I checked my triming. I thought I was doing 480p 4:3 aspect ratio...using the 5th edition of the book, figure 4.9, JUST as it states. I do the math on the aspect ratio, and it's wrong, or I am not understanding these diagrams:


Figure 4.9 is Video Demystified:


"Figure 4.9. 480p Analog-Digital Relationship (4:3 Aspect Ratio, 59.94 Hz, 27 MHz Sample Clock).


so I designed an embedded module wityh this timing:


0-137:  Send EAV, 0x80, 0x10.... SAV)

138-857: Send Data


It states that on this figure, this aspect ratio is 4:3, as I needed.  So I did the following math:


480 x (4/3) = 640, so I am sending something totally different. Is this figure wrong? Or am I missing something? I also checked some of the others, and they are also like this...the timing they show does not match the aspect ratios they state. There's got to be a detail I am missing because I just can't see a publisher making a mistake like this.


OK, so lets say I am wrong: My goal is to implement 480p (848 x 480).


What kind of timing so I use for blanking? So I use the {0x80,0x10} for blanking?I am currently also using figure 4.13, which I think is accurate?


ALSO, I am using one of the microblaze CPU's in the FPGA to do the I2C setup:


static Xuint8 ADV7511InitRegSet1[ADV7511_INIT_REG_SET1_LENGTH][2] =


                    {0x01,          0x00},          //          Set N Value(6144)

                    {0x02,          0x18},          //          Set N Value(6144)

                    {0x03,          0x00},          //          Set N Value(6144)

                    {0x15,          0x00},          //          24-bit, 444 YPrPb input

                    {0x16,          0x60},          //          YPrPb 444

                    {0x17,          0x00},          //          DE Generation Disabled

                    {0x18,          0x46},          //          CSC disabled

                    {0x40,          0x80},          //          General Control packet enable

                    {0x41,          0x10},          //          Power down control

                    {0x48,          0x08},          //          Data left justified

                    {0x49,          0xA8},           //          Set Dither_mode - 12-to-10 bit

                    {0x4C,          0x00},          //          8 bit Output

                    {0x55,          0x40},          //          Set YCrCb 444 in AVinfo Frame

                    {0x56,          0x08},          //          Set active format Aspect

                    {0x96,          0x20},          //          HPD Interrupt clear

                    {0x98,          0x03},          //          ADI Recommended Write

                    {0x99,          0x02},          //          ADI Recommended Write

                    {0x9C,          0x30},          //          PLL Filter R1 Value

                    {0x9D,          0x61},          //          Set clock divide

                    {0xA2,          0xA4},          //          ADI Recommended Write

                    {0xA3,          0xA4},          //          ADI Recommended Write

                    {0xA5,          0x44},          //          ADI Recommended Write

                    {0xAB,          0x40},          //          ADI Recommended Write

                    {0xAF,          0x16},          //          Set HDMI Mode

                    {0xBA,          0x60},          //          No clock delay

                    {0xD1,          0xFF},          //          ADI Recommended Write

                    {0xDE,          0x9C},          //          ADI Recommended Write

                    {0xE4,           0x60}          //          VCO_Swing_Reference_Voltage



static Xuint8 ADV7511InitRegSet3[ADV7511_INIT_REG_SET3_LENGTH][2] =


                    {0x15,          0x02},          //          Input id = 2, 4:2:2

                    {0x16,          0x79},          //          8 bits, Style 1

                    {0x48,          0x10},          //          Video Input Justification = 10 (left justified)

                    {0x17,          0x61},          //          Gen DE



//                    Embedded Sync Processing Settings for 480p:

                    {0x30,          0x04},          // R0x30[7:0] = Hsync Placement [9:2] (Embedded Sync Decoder)

                    {0x31,          0x03},          // R0x31[7:6] = Hsync Placement [1:0] (Embedded Sync Decoder)

                                                            // R0x31[5:0] = Hsync Duration  [9:4] (Embedded Sync Decoder)

                    {0x32,          0xE0},          // R0x32[7:4] = Hsync Duration  [3:0] (Embedded Sync Decoder)

                                                            // R0x32[3:0] = Vsync Placement [9:6] (Embedded Sync Decoder)

                    {0x33,          0x24},          // R0x33[7:2] = Vsync Placement [5:0] (Embedded Sync Decoder)

                                                            // R0x33[1:0] = Vsync Duration  [9:8] (Embedded Sync Decoder)

                    {0x34,          0x06},          // R0x34[7:0] = Vsync Duration  [7:0] (Embedded Sync Decoder)



//                    DE Generation Settings for 480p:

                    {0x35,          0x1E},          // R0x35[7:0] = DE Generation Hsync Delay[9:2] (In Pixels)

                    {0x36,          0x64},          // R0x36[7:6] = DE Generation Hsync Delay[1:0] (In Pixels)

                                                            // R0x36[5:0] = Vsync Delay for DE Generation. (In Hsyncs)

                    {0x37,          0x05},          // R0x37[7:4] = Interlace Offset For DE Generation

                                                            // R0x37[3:0] =

                    {0x38,          0xA0},          // R0x38[7:2] =

                                                            // R0x38[1:0] =

                    {0x39,          0x1E},          // R0x39[7:0] =

                    {0x3A,          0x00},          // N/A



//                    Sync Adjustment Settings for 480p:

                    {0xD7,          0x04},

                    {0xD8,          0x03},

                    {0xD9,          0xE0},

                    {0xDA,          0x24},

                    {0xDB,          0x06},

                    {0xDC,          0x00},

                    {0xDD,          0x00},

                    {0xFA,          0x00},

                    {0xFB,          0x00}