Viewing the following picture i have several question about the EDK Connections, i hope somebody could help me:
1. In the AXI Stream Bus, why is it a clk of 200MHz? Is it a specification of the ADC and DAC?.
2. The ADC is connected with a DMA, and DAC with a VDMA, the VDMA is obligatory? May i exchange it with a DMA like ADC?
3. If i connected a DMA with DAC, the vdma_clk is similar dma_clk no?
4. What is the meaning of delay_clk?
5. Are there any specification of the PCORE's ports?