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AD9915 internal PLL not locked

Question asked by Andre.K on Apr 4, 2013
Latest reply on Apr 5, 2013 by DSB

I'm trying to use single ended source for the REF_CLK input according Figure33-c (datasheet page 21). The VCO filter is designed according the Evaluation board schematic. PLL enabled, VCO calibrated. Frequency of source is 25MHz, the N divider is set to 100 value (to achieve sysclk 2500MHz). When the EXT_POWER_DOWN pin is 1 - the bit 24(USR0 register) shows 1, but when the EXT_POWER_DOWN pin is 0 the bit 24(USR0 register) shows 0, at the output of DDS (AOUT) is the sinus signal, at the SYNC_CLK pin is signal about 150MHz(rather unstable) and the DDS case starts heating. Does anybody know why the PLL is not locked? Thanks

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