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ADF4360-7. Noise and two sorts of loss of lock due to layout?

Question asked by temok on Apr 4, 2013
Latest reply on Apr 5, 2013 by Brigid.Duggan

I've been using ADF4360-7 in several designs and found the component easy to work with. In the latest design an ADF4360-7 shows a noisy signal, frequent short loss of lock and longer loss of lock in intervals from ms to minute.

The ref frequency is a 16.3681MHz crystal with a clipped sinus 0.9Vpp output. ADIsimPLL was used for the design of a fixed frequency output of 380.556MHs. Power supply is 3V well regulated. Nominal settings are:

C reg: 0000 1111 1100 0001 0010 0000

N reg: 0000 0000 0101 1101 0000 0010

R reg: 0000 0000 0000 0000 1000 0001

L1 and L2 are 27nH shunted with 470 Ohm resistors.

The SNR in the output is approx 70dB/Hz at 50kHz from peak, the noise is a broad bell shape from wich the peak emerges. The digital lock output has short loss of lock at varying sub second intervals, at the same time Vtune has a small 'disturbance'. At longer intervals there is a more serious loss of lock where Vtune goes almost to ground before resuming normal operation.

After looking at obvious sources of problems (also varying component values in the charge pump filter but without positive results) we muxed out the R counter and N counter. The N counter appears to be stable at 2us intervals. The R counter also has 2us intervals but misses one pulse at the outset of the 'serious' loss of lock (but appears to be unaffected at the small lass of of lock).

We also muxed out the DVdd signal and found that it gave the same output as Digital Lock, what does the DVdd output really show? I doubt we have an internal loss of power supply. Anyway the chip power supply is stable, we see no glitches at any time.

 

Now we have a similar board with exactly the same settings (but with a somewhat different board layout) that locks properly (although we may have more noise than expected). Any suggestions on how to get the new design to lock (with an acceptable noise floor)?

Is the loss of lock due to noise, in that case where?

 

Image shows in yellow the R counter output (noise on this signal is due to the MUX output being routed to sa standard test point) and in blue Vtune. Notice the missing R counter pulse.

F0000TEK.JPG

 

Image below shows an instance of a small disturbance of Vtune. Signal traces as in image above.

F0001TEK.JPG

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