I am facing AD7192 analog inputs (AIN1 ... AIN 4) current flow out problem.
The attachment is my ADC schematic design. The ADC SPI pins are controlled by Altera CPLD.
May I know why there's current flow out from analog inputs from AD7192? I using default AD7192 register setting, where the buffer is ON.
Any suggestion for my schematic design if I use Altera CPLD to control AD7192?