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AD7876 track/hold and conversion time

Question asked by ianstedman on Apr 2, 2013
Latest reply on Apr 30, 2013 by Smann

Hello,

 

Hopefully I have posted this in the correct sub-forum.

 

I am currently investigating an issue with one of our older products that uses the AD7876 ADC. At -40C we see +/- full scale readings, when we expect normal results (analogue range is scaled +/-11V). Checking the timing of the ADC and the input voltage, I observed an anomaly.

The control logic for the ADC, switches the long multiplexer chain, 400ns after the CONVSTART signal goes low, to initialise the conversion.

Will the change of input and resulant noise spike, upset the hold amplifier of the ADC?

 

The datasheet for the AD7876, states a 2us hold time, our design appears to change the input too soon.

tek00008.png

Also, the CS/CONVSTART signal is driven low for 7.8us by the controlling FPGA, the busy signal is ignored. The datasheet states a conversion time of 6.5 to 9us (for internal reference clock). If we are not waiting long enough for the conversion to complete, will this cause results that are either 000h or 3FFh?

 

Any help appreciated.

 

Ian

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